Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
“Assist features” in masks may be used to improve the image projected onto the resist and ultimately the developed device. Assist features are features that are not intended to appear in the pattern developed in the resist but are provided in the mask to take advantage of diffraction effects so that the developed image more closely resembles the desired circuit pattern. Assist features are generally “sub-resolution” or “deep sub-resolution,” meaning that they are smaller in at least one dimension than the smallest feature in the mask that will actually be resolved on the wafer. Assist features may have dimensions defined as fractions of the critical dimension. In other words, because the mask pattern is generally projected with a magnification of less than 1, e.g., ¼ or ⅕, the assist feature on the mask may have a physical dimension larger than the smallest feature on the wafer.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask), which is improved with the use of assist features. Placement of these assist features generally follows a pre-defined set of rules. Following this method, designers determine how to bias a line, for example, and placement of assist features is determined in accordance with a set of predetermined rules. When creating the set of rules, test masks are exposed to different illumination settings and NA settings, which are repeated. Based on the set of test masks, a set of rules is created for assist feature placement.
However, these rules are generated based on a one-dimensional analysis or a one-and-a-half-dimensional analysis. Rules generated utilizing a one-dimensional analysis are based on an analysis of parallel lines. Rules generated utilizing a one-and-a-half-dimensional analysis take into consideration spacing between two parallel lines, line width and lines in the vicinity of the parallel lines. The one-and-half-dimensional approach is often useful for non-uniform pitch between parallel lines. Obviously, the more factors considered, the more complex the rules become.
The rules-based approach does not adapt itself well to complicated designs where a two-dimensional analysis is preferred. A two-dimensional analysis is based on all of the factors considered in the one-dimensional analysis and the one-and-a-half dimensional analysis, but is further based on a full analysis of the surroundings, i.e., an analysis of the full design layout or any portion thereof. As a result, rules based on a two-dimensional analysis are very difficult to formulate and express, and generally lead to very complicated multi-dimensional matrices. Often designers prefer to use a one-dimensional or one-and-a-half dimensional approach.
In a pending application, namely, U.S. patent application Ser. No. 10/756,830 filed on Jan. 14, 2004, which is hereby incorporated by reference in its entirety, the applicants disclosed a simple method for generating assist features which takes into account a full analysis of the surroundings of the features to be imaged. More specifically, the applicants disclosed a method for utilizing an interference map to identify “seeding” sites which define where to place assist features or scattering bars (SB) within the mask design. While this method allows for the reliable generation of SB for the full-chip data processing, the lithography printing performance utilized when generating the interference map is assumed to be the best focus setting.
However, for IC design rules (expressed in half feature pitch) beyond one-third of illumination wavelength, λ, such as 45 nm and 32 nm technology nodes, conventional optics (numerical aperture, or NA<1) can no longer attain sufficient resolution and the desired depth of focus (DOF) for lithography manufacturing. Hyper NA optics (i.e. NA>1) or a lens in the exposure tool with numerical aperture greater than 1.0 have been proposed for IC manufacturing. In theory, hyper NA can be achieved when the printing medium is not under air (with refraction index, n, around 1.0) but under a medium, such as water, that has a refraction, n, greater than the one in air, or n>1.0.
Using immersion lithography with hyper NA enables the printing of features at one-fourth of illumination wavelength, per the following equation:Resolution (or half-pitch CD)=k1[(λ/n)/NA]  (1)Assuming k1˜0.3, achievable using phase-shifted mask (PSM) together with optical proximity correction (OPC), 193 nm exposure wavelength, immersion with water (n=1.43 for 193 nm), with NA=1.2, it is theoretically feasible to print half pitch feature CD˜33 nm. The corresponded DOF can be calculated as:DOF=k2[(λ)*(n)/(NA)2]  (2)Given the same printing condition, for k2˜1.0 that is typically assumed for printing lines and spaces, the theoretical DOF expected is about 190 nm, or less than 0.2 μm. This is barely adequate from the point of view of focal plane leveling capability limit with advanced mechanical wafer stage.
For printing a contact hole mask, the typical k2 may be half of the achievable one for printing lines and spaces. At k2˜0.5, the estimated DOF is no better than 0.1 μm, which is not good. Using linear polarized illumination perhaps can improve k2 since it can enhance aerial image contrast for the directional 1D features, such as lines and spaces. However, contact hole patterns are more or less a type of 2D structure.
Thus, as the desired critical dimensions (CD) of features continue to decrease, it is necessary to prevent the degradation of the DOF so as to allow the printing of features having such reduced CDs in a practical manufacturing process.